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Information Equipment LSIs
MN5814
TFT AV Panel Controller IC
s Overview
The MN5814 is a TFT LCD panel timing controller IC.
VCOI VDD QVDZMSEL PD POSSET JUST HDOT2 CPH1 RL CPH2 STV2 CPH3
s Features
* Supports both composite sync and separate sync signal video inputs. * Horizontal and vertical position adjustment function Horizontal: 5 bits (Adjustment range: 9.38 s) Vertical: 4 bits (Adjustment range: 14 H) * Supports multiple panel types From 2.5-type to 7-type wide-screen panels For wide-screen panels: Display with black side bands (3 modes) Just-fit display Zoom (2 modes) * Switching between PAL and NTSC (PAL: decimation only) * Underside on-screen display (UONS) * An optimal zooming mode is possible according to the display panel through 2-zooming mode of ZOOM1 and ZOOM2. * UONS display at arbitrary positions is possible by the black side control pins. Also provides full-screen black side display.
VCOO VSS RESET HDOT1 WH (UONS) HPOS4 HPOS3 HPOS2 HPOS1 NP1 VDD VSS
36 35 34 33 32 31 30 29 28 27 26 25
37 38 39 40 41 42 43 44 45 46 47 48
1 2 3 4 5 6 7 8 9 10 11 12
24 23 22 21 20 19 18 17 16 15 14 13
STH2 STH1 QH (ZOOMC) OEH STV1 OEV1 OEV2 OEV3 CPV INTEXT POL UD
(TOP VIEW) Note: Pin names in parentheses apply for use with the 1,200 and 1,440 stripe panel types.
s Applications
* TFT LCD panels
Publication date: August 2001
SDF00021AEM
SYNCIN HSYNCIN CPHSEL (SIDE2) QHSEL (SIDE1) VDBIN HOUT VOUT BLACK VPOS3 VPOS2 VPOS1 LIBOX (ZOOM)
1
MN5814
HSYNCIN
SYNCIN
INTEXT
s Block Diagram
2
VCOO OEH VCOI
RL
HC_OEH
HOUT
QHSEL CPHSEL HPOS1 HPOS2 HPOS3 HPOS4 POSSET VPOS1 VPOS2 VPOS3 HDOT1 HDOT2 JUST ZOOM UONS NP1 UD RESET
MS_DTYP, MS_QH MS_CPH MS_MODE MS_DOT MS_NRESET MS_DOT_HC [2 :0] MS_UONS MS_NWH MS_RL
PD
TP_HGOCOUNT TP_HGOPER HC_HCOUNT2 HC_OEH
IH_ PDCONT
IH_PD
Phase comparison block (IH)
PO_QH D_VCO MS_ DOT NL_ VOUT MS_ NRESET VC_UO NST MS_UO NS MS_NR ESET
Equalization pulse removal block (TP)
Oscillator cell
I_VCOI
Division control block (D)
MS_DOT
D_VCO
VC_VOUT
FH_OEV3
MS_NRESET
D_VCO
MS_UONS
MS_RL
MS_HPOS
FH_OEV2 FH_FIELD HC_OEV HC_WINDOW
OEV3 OEV2 OEV1
MS_NWH
FH_OEV1
MS_NRESET
HC_HCOUNT1
Mode settings block (MS)
TP_VDBIN
Field discrimination block (FH) Horizontal synchronization block (HC)
HC_OUT_MIN VC_VCOUNT VC_MABIKIEN VC_ZOOMEN VC_UONST HC_OEH_NOM
MS_ NRESET
D_VCO
SDF00021AEM
TASOJIS1 MS_MODE ZO_OEV1 OEV3 HC_POLSET MS_PONRESET MS_DTYP, MS_QH HC_OEH MS_DOT MS_DOT MS_NRESET MS_ZOTYP MS_UONS HC_OEH D_VCO
HC_CPV VC_UONST ZO_ZOOMC VC_ISTV TASOJIS1 VC_VOUT VDBIN QVDZMSEL
CPV BLACK
VC_VOUT
VC_VOUT VDBIN
D_VCO
TP_VOBIN INTEXT HC_HALF
MS_VPOS, MSBFVPOS
MS_NRESET
FH_FIELD
MS_UD
TP_IHDBIN
NL_OEV1 OEV3
HC_HCOUNT3
QVD selection block (NL)
MS_NRESET
MS_NWH
MS_DOT
D_VCO
Polarity control block (PO)
Vertical synchronization block (VC)
VC_STV_LTBOX
Line decimation/Zoom correction block (ZO)
VDBIN
POL
CPV
STH1
STH2
STV1
STV2
VOUT
QVDZMSEL
MN5814
s Pin Descriptions
Pin No. 1 2 3 Pin Name SYNCIN HSYNCIN CPHSEL (SIDE2) QHSEL (SIDE1) VDBIN HOUT VOUT BLACK VPOS3 VPOS2 VPOS1 LTBOX (ZOOM) I/O I I I Composite sync input Horizontal sync input (separate) In 1,440 or 1,200-stripe mode: Black side and just-fit control In 960-stripe mode: Disabled In 480 or 960-delta mode: CPH pulse phase switching In 1,440 or 1,200-stripe mode: Black side and just-fit control In 960-stripe mode: Disabled In 480 or 960-delta mode: QH pulse phase switching Vertical sync input (separate) Horizontal sync output Vertical sync output Black signal output Vertical display position switching (STV1 and STV2 position switching) Description
4
I
5 6 7 8 9 10 11 12
I O O O I I I I
High: Zoom or letterbox display In 1,440 or 1,200-mode: Zoom display control In 480 or 960-delta or 960-stripe mode: Letterbox display control Up/down scan direction switching (STV1 and STV2 output switching) Video, opposite electrode reversal signal Composite/separate input switching Gate driver IC clock Gate driver IC output stage enable pulse signals
13 14 15 16 17 18 19 20 21 22
UD POL INTEXT CPV OEV3 OEV2 OEV1 STV1 OEH QH (ZOOMC) STH1 STH2 CPH3 STV2 CPH2 RL
1 O I O O O O O O O
Gate driver IC start pulse 1 Source driver IC output stage enable pulse signal In 480 or 960-delta mode: Color arrangement switching pulse In 1,200 or 1,440-mode: Zoom control pulse In 960 stripe mode: Fixed low-level output Source driver IC start pulse 1 Source driver IC start pulse 2 Source driver IC clock 3 Source driver IC start pulse 2 Source driver IC clock 2 Left/right scan direction switching (STH1 and STH2 output switching)
23 24 25 26 27 28
O O O O O I
SDF00021AEM
3
MN5814
s Pin Descriptions (continued)
Pin No. 29 30 31 32 33 34 Pin Name CPH1 HDOT2 JUST POSSET PD QVDZMSEL I/O O I I I O I Source driver IC clock 1 Display pixel count mode switch 2 In 1,200 or 1,440-mode: Just-fit display switching In 960-mode: Stripe/delta control Horizontal/vertical display position offset switching Phase comparator output In 480 or 960-delta or stripe mode: QVD input In 1,200 or 1,400-mode: Zoom 1/zoom 2 display switching OEV pulse control in zoom mode Power supply (VDD) VCO input (system clock input) VCO output Ground (GND) System reset Display pixel count mode switching 1 In 1,200 or 1,440-mode: "Under on-screen" display control In 480 or 960-delta or stripe mode: WH (write/hold) control Horizontal display position switching signals (STH1 and STH2 position switching) Description
35 36 37 38 39 40 41 42 43 44 45 46 47 48
VDD VCOI VCOO VSS RESET HDOT1 WH (UONS) HPOS4 HPOS3 HPOS2 HPOS1 NP1 VDD VSS
I I O I I I I I I I I I I I
NTSC/PAL switching Power supply (VDD) Ground (GND)
4
SDF00021AEM
MN5814
s Electrical Characteristics
1. Absolute Maximum Ratings at VSS = 0 V Parameter Supply voltage Input pin voltage Output pin voltage Output current (HL2 pins) Output current (HL4 pins) Power dissipation Operating temperature Storage temperature Symbol VDD VI VO IO IO PD Topr Tstg Rating - 0.3 to +4.6 - 0.3 to VDD+0.3 - 0.3 to VDD+0.3 6 12 330 -40 to +85 -55 to +150 Unit V V V mA mA mW C C
Note) 1. HL2 pins: QH, CPV, OEH, OEV1 to OEV3, POL, STH1, STH2, STV1, STV2, HOUT, VOUT, BLACK HL4 pins: PD, CPH1 to CPH3 2. The absolute maximum ratings are limit values for stresses applied to the chip so that the chip will not be destroyed. Operation is not guaranteed within these ranges. 3. All the VDD and VSS pins must be connected externally to the corresponding power or ground. 4. The power dissipation rating applies at T opr = 85C when the MN5814 is mounted on a glass-epoxy printed circuit board. The actual value differs depending on the printed circuit board used and the thermal conditions in the end product.
2. Recommended Operating Conditions at VSS = 0 V Parameter Supply voltage Ambient temperature Input rise time Input fall time Oscillator frequency Recommended values for external capacitors Symbol VDD Ta tr tf fOSC1 CXI90 CXO90 30 MHz Xtal VDD = 3.3 V, with an external feedback resistor VI = VDD or VSS , VDD = 3.3 V
XI XO
Condition
Min 2.7 -40 0 0
Typ 3.3 30 33
(15 MHz to 25 MHz)
Max 3.6 85 100 100
Unit V C ns ns MHz pF
10
(25 MHz to 40 MHz)
Recommended values for external resistors
Rf90
2.2
k
Rf CXO
CXI
Note) Since the oscillator characteristics differ depending on the oscillator element used and the external capacitor conditions, consult the manufacturer of the oscillator element to determine the optimal oscillator circuit.
SDF00021AEM
5
MN5814
s Electrical Characteristics (continued)
3. Electrical Characteristics at VDD = 2.7 V to 3.6 V, VSS = 0 V, fTEST = 30 MHz, Ta = -40C to +85C Parameter Quiescent supply current Symbol IDDS Condition VI (pulled-up pins) = OPEN, VI (pulled-down pins) = OPEN, VI (XI) = VDD *, With either the VDD or the VSS level applied simultaneously to all of the other input pins and I/O pins in the high-impedance state. Operating supply current IDDO VI = VDD or VSS , f = 30 MHz, VDD = 3.3 V, outputs open VDD = 2.7 V to 3.6 V VI = VDD or VSS 15 30 mA Min Typ Max 500 Unit A
1) CMOS input level Schmitt trigger pins: RESET, VDBIN, SYNCIN, HSYNCIN Input threshold voltage VT+ VT- Input leakage current ILI VDD x 0.3 VDD x 0.7 0 VI = 0 V VI = VDD 33 1.85 1.45 100 VDD x 0.7 5 A V
2) CMOS input level pins with built-in pull-up resistor: RL, UD, HDOT1, HDOT2, INTEXT High-level input voltage Low-level input voltage Pull-up resistor Input leakage current VIH VIL RIH ILIH VDD VDD x 0.3 318 10 V V k A
3) CMOS input level pins with built-in pull-down resistor: NP1, HPOS1 to HPOS4, JUST, UONS, VPOS1 to VPOS3, ZOOM, QHSEL, CPHSEL, POSSET, QVDZMSEL High-level input voltage Low-level input voltage Pull-down resistor Input leakage current VIH VIL RIL ILIL VOH VOL VI = VDD VI = VSS IOH = -1.9 mA, VI = VDD or VSS IOL = 1.9 mA, VI = VDD or VSS IOH = -3.8 mA, VI = VDD or VSS IOL = 3.8 mA, VI = VDD or VSS VDD x 0.7 0 33 VDD - 0.6 100 VDD VDD x 0.3 318 10 0.4 V V k A
4) Push-pull output pins: QH, CPV, OEH, OEV1 to OEV3, POL, HOUT, VOUT, BLACK High-level output voltage Low-level output voltage V V
5) Push-pull output pins: CPH1 to CPH3 High-level output voltage Low-level output voltage VOH VOL VDD - 0.6 0.4 V V
Note) *: The IDDS associated with the VDD applied to the oscillator pin XI shall be take from a power supply separate from the measured power supply.
6
SDF00021AEM
MN5814
s Electrical Characteristics (continued)
3. Electrical Characteristics at VDD = 2.7 V to 3.6 V, VSS = 0 V, fTEST = 30 MHz, Ta = -40C to +85C (continued) Parameter Symbol Condition IOH = -1.9 mA, VI = VDD or VSS IOL = 1.9 mA, VI = VDD or VSS VO = High-impedance state, VI = VDD or VSS , VO = VDD or VSS IOH = -3.8 mA, VI = VDD or VSS IOL = 3.8 mA, VI = VDD or VSS VO = High-impedance state, VI = VDD or VSS , VO = VDD or VSS Min VDD - 0.6 Typ Max 0.4 5 Unit 6) Tristate output pins: STH1, STH2, STV1, STV2 High-level output voltage Low-level output voltage Output leakage current VOH VOL ILO V V A
7) Tristate output pins: PD High-level output voltage Low-level output voltage Output leakage current VOH VOL ILO VDD - 0.6 0.4 5 V V A
s Package Dimensions (Units: mm)
* TQFP048-P-0707B
9.000.20 7.000.10 36 25
37
24
(0.75)
7.000.10
48
13
1 (0.75) 0.50
1.20 max.
12 0.200.05
0.10 M
(1.00)
9.000.20
(1.00)
0.150.05
0.10
0.10
Seating plane
+0.10 -0.05
0 to 8 0.500.10
SDF00021AEM
7
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A. These materials are intended as a reference to assist customers with the selection of Panasonic semiconductor products best suited to their applications. Due to modification or other reasons, any information contained in this material, such as available product types, technical data, and so on, is subject to change without notice. Customers are advised to contact our semiconductor sales office and obtain the latest information before starting precise technical research and/or purchasing activities. B. Panasonic is endeavoring to continually improve the quality and reliability of these materials but there is always the possibility that further rectifications will be required in the future. Therefore, Panasonic will not assume any liability for any damages arising from any errors etc. that may appear in this material. C. These materials are solely intended for a customer's individual use. Therefore, without the prior written approval of Panasonic, any other use such as reproducing, selling, or distributing this material to a third party, via the Internet or in any other way, is prohibited.
2001 MAR

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